Currently semiconductor devices are requiring higher current densities in order to obtain higher performance. In addition, device dimensions are shrinking to geometries that are becoming increasingly problematic when conducting these higher current densities. The higher current densities and shrinking geometries must be accommodated in the art while simultaneously maintaining adequate levels of resistance to electromigration (EM), reduced metal voiding, improved wafer manufacturing throughput, while also avoiding other common reliability problems. While aluminum is a mature integrated circuit (IC) interconnect material, copper is a relatively new material for use in IC interconnects.
One of the most promising methods for depositing copper (Cu) on a substrate is through use of plating methods, such as electroplating. Electroplated copper provides several advantages over aluminum when used in integrated circuit (IC) applications, where a primary advantage is that copper is less resistive than aluminum-based materials and therefore capable of higher frequencies of operation. In addition, copper is more resistive to conventional problems associated with electromigration (EM) than is aluminum. The increased resistance to electromigration that is present when using copper provides an overall improvement in the reliability of semiconductor devices because, over time, circuits which have higher current densities and/or lower resistance to EM will have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits can cause the device to catastrophically fail in the field or during burn-in.
However, the integration of copper into the IC manufacturing process also introduces new problems, and is by no means completely optimized in terms of reliability or for high volume production. For example, it has been found that if copper is deposited too quickly into high aspect ratio openings using an electroplated bath that has a very high applied current or potential, substantially only in the direct current (DC) mode, problems are encountered with void regions or keyholes being formed in the copper interconnect. In these plating conditions, the deposited copper eventually pinches off at upper portions of the opening to create a copper-encapsulated air region or void in the incrementally-deposited copper film. Also, high current density, DC mode, plating of copper results in high deposition rates and produces a copper film that has degraded resistance to electromigration (EM) due to poor incorporation of electroplating impurities into the plated Cu film.
In addition, effective electroplating of the copper is highly dependent upon the quality of the underlying film. If the underlying copper seed film is not uniformly deposited or contains regions with insufficient amounts of seed material, the copper will not uniformly deposit in these areas and may cause reduction in IC yield and/or IC reliability issues. Typically, the copper plating's sensitivity to underlying seed layer quality increased when using low throughput, low DC plating methodologies. Therefore, regardless of whether high or low DC methods are used, one or more serious copper plating problems seem to be unavoidable in the final structure.
Therefore, a method for electroplating copper interconnects with adequate manufacturing throughput while simultaneously ensuring reduced or eliminated void formation, improved resistance to electromigration (EM), improved uniformity, and/or like advantages is needed in the semiconductor industry.
In addition to electroplating reliability, performance, and yield problems, conventional methods for depositing copper generally require electroplating the copper on the substrate using a fixed time deposition. Typically, a test wafer is processed through the electroplating chamber under specified conditions to determine if the process is operating within specification or control limits. If the system is operating within its limits, fixed time deposition processing of subsequent product wafers can begin for a period of time. This test wafer process control method assumes that subsequent product wafers will be in specification or within control limits by virtue of the assumption that the deposition conditions will hopefully remain unchanged over time.
The overall method of processing test wafers, determining static conditions by which the test wafers obtains good results, and then processing the wafer statically by these conditions with the hope of continued success is both time consuming, unreliable, and expensive. Therefore, it would be beneficial to provide copper electroplating systems which could in-situ endpoint or monitor electroplating operations in real time so that plating operations can be computer controlled dynamically during plating whereby test wafer usage and wafer scrap is reduced, throughput is further optimized, and film performance is improved.